Billions of IP in Silicon

Silicon Proven IP in 7LPP
Easy Migration to SF5A
Differentiated Low Power PCI Gen4 IP
Area and power optimized Gen3 PHY
PIPE compliant PHY integrates easily with industry standard controllers

Analog Bits and Samsung -

SF5A & 7LPP

 

Analog Bits and Samsung and our mutual customers have collaborated to offer a unique low power PCI Gen3/4 SERDES on Samsung 7LPP. These SERDES are low-power multi-rate, multi-protocol and optimized for area and power. The SERDES IP’s have been tape-out in silicon and silicon characterization are available. The SERDES IP is layout compatible to SF5A process.

Additionally, Analog Bits and Samsung will be offering PVT Sensor in SF5A process to our mutual foundry customers.

Stay tuned for more advanced IP’s that will be made available in SF5A.

More Analog Bits IPs

Benefits of this advanced node collaboration

    • Silicon Proven IP in 7LPP
    • Easy Migration to SF5A
    • Differentiated Low Power PCI Gen4 IP
    • Area and power optimized Gen3 PHY
    • PIPE compliant PHY integrates easily with industry standard controllers

Some new and novelty IP’s we have in SF5A & 7LPP

    • Low Power and Optimized for Performance PCIe SERDES
    • PLL IP’s:
      • Core Power Pinless PLL and Ref Clock PLL’s available upon request
    • Sensor IP’s:
      • PVT Sensor available and Power Supply Sensors available upon request

We trust you will find the following product datasheets helpful. Please feel free to contact us for your SoC IP needs.

We look forward to being your SF5A and 7LPP IP Partner.

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Product Datasheets for Samsung - SF5A & 7LPP

 

Select processes and nodes below. Results will display below the selector box. Click to download, or right click to open the datasheet in a new browser tab or window.

You must be logged in to download or view the product datasheets. If you already have an account, please log in here. New users should register an account.